Dirk Koch

Dirk Koch

Dr

 https://orcid.org/0000-0002-2568-4432
Filter
Conference contribution

Search results

  • 2022

    Precise Characterizing of FPGAs in Production Systems

    Babaei, B. & Koch, D., Sept 2022, 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). Washington, D.C.: IEEE, p. 464-465 2 p. (International Conference on Field-programmable Logic and Applications (Online)).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Tunable Fine-grained Clock Phase-shifting for FPGAs

    Babaei, B. & Koch, D., Sept 2022, 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). Piscataway, NJ: IEEE, p. 384-390 7 p. (International Conference on Field-programmable Logic and Applications (Online)).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • 2020

    Demo: A Closer Look at Malicious Bitstreams

    La, T., Mätas, K., Powell, J., Pham, K. & Koch, D., 2020, (Accepted/In press) 30th International Conference on Field-Programmable Logic and Applications (FPL).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond

    Mätas, K., La, T., Grunchevski, N., Pham, K. & Koch, D., 2020, 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    2083 Downloads (Pure)

  • Memristor-based Reconfigurable Circuits: Challenges in Implementation

    Dao, N. & Koch, D., 2 Apr 2020, IEEE Xplore. 6 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation

    Pham, K., Koch, D., Vaishnav, A., Georgopoulos, K., Malakonakis, P., Ioannou, A. & Mavroidis, I., 2 Nov 2020, (Accepted/In press) 2020 International Conference on Field-Programmable Technology (ICFPT). Maui, Hawaii, US

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Powerhammering through Glitch Amplification – Attacks and Mitigation

    Mätas, K., La, T., Pham, K. & Koch, D., 1 May 2020, Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020. p. 65-69 5 p. 9114608. (Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    276 Downloads (Pure)

  • Resource Elastic Database Acceleration

    Manev, K. & Koch, D., 4 Sept 2020, 30th International Conference on Field Programmable Logic and Application (FPL). Gothenburg, Sweden

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    167 Downloads (Pure)

  • Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms

    La, T., Mätas, K., Pham, K. & Koch, D., 2020, (Accepted/In press) 30th International Conference on Field-Programmable Logic and Applications (FPL).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    201 Downloads (Pure)
  • 2019

    EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

    Pham, K., Vesper, M., Koch, D. & Hung, E., 13 Jun 2019, The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    416 Downloads (Pure)

  • Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures

    Vaishnav, A., Pham, K. & Koch, D., 6 Jun 2019, 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART). ACM Digital Library

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Live Migration for OpenCL FPGA Accelerators

    Vaishnav, A., Pham, K. & Koch, D., 20 Jul 2019, International Conference on Field-Programmable Technology (FPT). Naha, Okinawa, Japan: IEEE, 8 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    316 Downloads (Pure)

  • Scalable Filtering Modules for Database Acceleration on FPGAs

    Manev, K., Vaishnav, A., Kritikakis, C. & Koch, D., 4 May 2019, (Accepted/In press) 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • The FOS (FPGA Operating System) Demo

    Vaishnav, A., Pham, K., Manev, K. & Koch, D., 22 May 2019, (Accepted/In press) 29th International Conference on Field Programmable Logic and Application (FPL). Barcelona, Spain

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    442 Downloads (Pure)

  • Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems

    Manev, K., Vaishnav, A. & Koch, D., 7 Oct 2019, (Accepted/In press) International Conference on Field-Programmable Technology (FPT).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    3136 Downloads (Pure)

  • ZUCL 2.0: Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs

    Pham, K., Paraskevas, K., Vaishnav, A., Attwood, A., Vesper, M. & Koch, D., 2019, FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers. VDE Verlag

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • ZUCL2.0 Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs

    Pham, K., Paraskevas, K., Vaishnav, A., Attwood, A., Vesper, M. & Koch, D., 7 Aug 2019, (Accepted/In press) Sixth International Workshop on FPGAs for Software Programmers (FSP 2019). VDE Verlag

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • 2018

    A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine

    Garcia Ordaz, J. R. & Koch, D., 2018, The 29th IEEE International Conference on Application-specific Systems, Architectures and Processors 2018.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    319 Downloads (Pure)

  • A Survey on FPGA Virtualization

    Vaishnav, A., Pham, K. & Koch, D., 21 May 2018, (Accepted/In press) 28th International Conference on Field Programmable Logic and Application (FPL). Dublin, Ireland, 8 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    2589 Downloads (Pure)

  • HLS Enabled Partially Reconfigurable Module Implementation

    Grigore, B., Koch, D. & Kritikakis, C., 2018, ARCS 2018. 12 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    390 Downloads (Pure)

  • IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

    Pham, K., Horta, E., Koch, D., Vaishnav, A. & Kuhn, T., 2018, IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2018).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    591 Downloads (Pure)

  • Resource Elastic Virtualization for FPGAs using OpenCL

    Vaishnav, A., Pham, K., Koch, D. & Garside, J., 6 Dec 2018, 28th International Conference on Field Programmable Logic and Application (FPL). Dublin, Ireland, 8 p. (International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    428 Downloads (Pure)

  • ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications

    Pham, K., Vaishnav, A., Vesper, M. & Koch, D., 2018, Fifth International Workshop on FPGAs for Software Programmers (FSP 2018) .

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • 2017

    Accelerating Linux Bash Commands on FPGAs Using Partial Reconfiguration

    Horta, E., Shen, X., Pham, K. & Koch, D., 26 Oct 2017, Proceedings of FPGAs for Software Programmers (FSP 2017) conference.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    164 Downloads (Pure)

  • A Security Library for FPGA Interlays

    Vaishnav, A., Garcia Ordaz, J. R. & Koch, D., 5 Oct 2017, International Conference on Field Programmable Logic and Applications (FPL). Ghent, Belgium: IEEE

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Asynchronous Interface FIFO Design on FPGA for High-throughput NRZ Synchronisation

    Liu, G., Garside, J., Furber, S., Plana, L. A. & Koch, D., 5 Oct 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 8 p. (International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    1633 Downloads (Pure)

  • HLS Compilation for CPU Interlays

    Garcia Ordaz, J. R. & Koch, D., 31 Dec 2017, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017) .

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    420 Downloads (Pure)

  • Making a Case for an ARM Cortex-A9 CPU Interlay Replacing the NEON SIMD Unit

    Garcia Ordaz, J. R. & Koch, D., 2017, International Conference on Field-Programmable Logic and Applications. (2017 27th International Conference on Field Programmable Logic and Applications (FPL)).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    415 Downloads (Pure)

  • On the HLS Design of Bit-Level Operations and Custom Data Types

    Garcia Ordaz, J. R. & Koch, D., 27 Oct 2017, International Workshop on FPGAs for Software Programmers.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    1668 Downloads (Pure)

  • PCIeHLS: an OpenCL HLS framework

    Vesper, M., Koch, D. & Pham, K., 29 Oct 2017, Proceedings of FPGAs for Software Programmers (FSP 2017) conference.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    188 Downloads (Pure)
  • 2016

    A partial reconfiguration controller for Altera Stratix V FPGAs

    Xiao, Z., Koch, D. & Lujan, M., 29 Aug 2016, 26th International Conference on Field Programmable Logic and Applications (FPL): FPL 2016. IEEE Computer Society , p. 1 4 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • ECOSCALE: Reconfigurable computing and runtime system for future exascale systems

    Mavroidis, I., Papaefstathiou, I., Lavagno, L., Nikolopoulos, D. S., Koch, D., Goodacre, J., Sourdis, I., Papaefstathiou, V., Coppola, M. & Palomino, M., 25 Apr 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. IEEE, p. 696-701 6 p. 7459398

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

    Vesper, M., Koch, D., Vipin, K. & Fahmy, S. A., 26 Sept 2016, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. IEEE, 7577334. (International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    392 Downloads (Pure)

  • Parallel Hardware Merge Sorter

    Song, W., Koch, D., Lujan, M. & Garside, J., 16 Aug 2016, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016. IEEE, p. 95-102 8 p. 7544757

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric

    Garcia Ordaz, J. R. & Koch, D., 28 Nov 2016, 2016 IEEE 27th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2016. IEEE, Vol. 2016-November. p. 229-230 2 p. 7760802

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    Open Access
    File
    371 Downloads (Pure)
  • 2015

    Placing partially reconfigurable stream processing applications on FPGAs

    Koch, D., Cheung, P. (Editor), Luk, W. (Editor) & Silvano, C. (Editor), 2 Sept 2015, Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015). Cheung, P., Luk, W. & Silvano, C. (eds.). IEEE, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • Rapid Overlay Builder for Xilinx FPGA

    Koch, D., Shannon, L. (Editor) & Andrews, D. (Editor), 2 May 2015, Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. Shannon, L. & Andrews, D. (eds.). IEEE Computer Society , Vol. 23. p. 17-20 4 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • 2014

    Hierarchical reconfiguration of FPGAs

    Koch, D. & Herkersdorf, A. (Editor), 2014, Proceedings of the 24th International Conference on Field Programmable Logic and Applications. Herkersdorf, A. (ed.). USA: IEEE, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

    File
    269 Downloads (Pure)

  • Portable module relocation and bitstream compression for Xilinx FPGAs

    Koch, D., Herkersdorf, A. (Editor), Wehn, N. (Editor) & Hubner, M. (Editor), Sept 2014, Proceedings of the 24th International Conference on Field Programmable Logic and Applications. Herkersdorf, A., Wehn, N. & Hubner, M. (eds.). USA: IEEE, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

  • 2013

    EasyPR — An easy usable open-source PR system

    Koch, D., Amano, H. (Editor), Ha, Y. (Editor) & Yamaguchi, Y. (Editor), Dec 2013, 2013 International Conference on Field-Programmable Technology (FPT). Amano, H., Ha, Y. & Yamaguchi, Y. (eds.). USA: IEEE, p. 414-417 4 p.

    Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review