3-D topologies for networks-on-chip

Vasilis F. Pavlidis, Eby G. Friedman

    Research output: Contribution to journalArticlepeer-review


    Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3-D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3-D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3-D NoC as compared to a traditional 2-D NoC topology for a network size of N= 128 and N = 256 nodes, respectively. © 2007 IEEE.
    Original languageEnglish
    Pages (from-to)1081-1090
    Number of pages9
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number10
    Publication statusPublished - Oct 2007


    • 3-D circuits
    • 3-D integrated circuits (ICs)
    • 3-D integration
    • Networks-on-chip (NoC)
    • Topologies


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