3.5-D integration: A case study

Shashikanth Bobba, Pierre Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


    Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred as 3-D TSV integration, and 3D monolithic integration. In this paper, we present a hybrid integration scheme that combines these two approaches, taking into account their existing technology limits, into a disruptive paradigm called 3.5-D integration. Our novel integration supports circuit-partitioning both at the gate and block level with unprecedented benefits in cost. To demonstrate the effectiveness of 3.5-D integration, we chose as case study a 288-core MPSoC and we made hypothesis on the manufacturing and test cost. We argue a potential 20% decrease in the manufacturing cost and 30% decrease in the test cost when compared to 3-D TSV integration. In order to study the performance improvement of the MPSoC, we benchmarked various blocks of the core and the on-chip interconnection network, connecting all the cores. Our study shows large improvement in performance of the core (average of 11.5%) and latency (average of 24%) of the Network-on-Chip (NoC) for the 3.5-D integration when compared to the corresponding 3-D TSV implementation.

    Original languageEnglish
    Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    Number of pages4
    Publication statusPublished - 2013
    Event2013 IEEE International Symposium on Circuits and Systems - Beijing, China
    Duration: 19 May 201323 May 2013


    Conference2013 IEEE International Symposium on Circuits and Systems
    Abbreviated titleISCAS 2013


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