A cellular processor array simulation and hardware prototyping tool

David R W Barr; Piotr Dudek

doi:10.1109/CNNA.2008.4588680

A cellular processor array simulation and hardware prototyping tool

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems. ©2008 IEEE.

Original language	English
Title of host publication	Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications\|Proc IEEE Int Workshop Cell Neural Networks Appl
Pages	213-218
Number of pages	5
DOIs	https://doi.org/10.1109/CNNA.2008.4588680
Publication status	Published - 2008
Event	2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures - Santiago de Compostela Duration: 1 Jul 2008 → …

Conference

Conference	2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures
City	Santiago de Compostela
Period	1/07/08 → …

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/CNNA.2008.4588680

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title = "A cellular processor array simulation and hardware prototyping tool",

abstract = "We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems. {\textcopyright}2008 IEEE.",

author = "Barr, {David R W} and Piotr Dudek",

note = "Best Paper Award; 2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures ; Conference date: 01-07-2008",

year = "2008",

doi = "10.1109/CNNA.2008.4588680",

language = "English",

isbn = "9781424420902",

pages = "213--218",

booktitle = "Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications|Proc IEEE Int Workshop Cell Neural Networks Appl",

}

Barr, DRW & Dudek, P 2008, A cellular processor array simulation and hardware prototyping tool. in Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications|Proc IEEE Int Workshop Cell Neural Networks Appl. pp. 213-218, 2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures, Santiago de Compostela, 1/07/08. https://doi.org/10.1109/CNNA.2008.4588680

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AU - Dudek, Piotr

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N2 - We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems. ©2008 IEEE.

AB - We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems. ©2008 IEEE.

U2 - 10.1109/CNNA.2008.4588680

DO - 10.1109/CNNA.2008.4588680

M3 - Conference contribution

SN - 9781424420902

SP - 213

EP - 218

BT - Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications|Proc IEEE Int Workshop Cell Neural Networks Appl

T2 - 2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures

Y2 - 1 July 2008

ER -

A cellular processor array simulation and hardware prototyping tool

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UN SDGs

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