A compact FPGA implementation of a bit-serial SIMD cellular processor array

Declan Walsh; Piotr Dudek

doi:10.1109/CNNA.2012.6331450

A compact FPGA implementation of a bit-serial SIMD cellular processor array

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 x 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated. © 2012 IEEE.

Original language	English
Title of host publication	International Workshop on Cellular Nanoscale Networks and their Applications\|Int. Workshop Cell. Nanoscale Netw. Appl.
DOIs	https://doi.org/10.1109/CNNA.2012.6331450
Publication status	Published - 2012
Event	2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 - Turin Duration: 1 Jul 2012 → …

Conference

Conference	2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
City	Turin
Period	1/07/12 → …

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10.1109/CNNA.2012.6331450

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title = "A compact FPGA implementation of a bit-serial SIMD cellular processor array",

abstract = "An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 x 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated. {\textcopyright} 2012 IEEE.",

author = "Declan Walsh and Piotr Dudek",

year = "2012",

doi = "10.1109/CNNA.2012.6331450",

language = "English",

isbn = "9781467302890",

booktitle = "International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl.",

note = "2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 ; Conference date: 01-07-2012",

}

Walsh, D & Dudek, P 2012, A compact FPGA implementation of a bit-serial SIMD cellular processor array. in International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl.. 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012, Turin, 1/07/12. https://doi.org/10.1109/CNNA.2012.6331450

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AU - Walsh, Declan

AU - Dudek, Piotr

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AB - An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 x 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated. © 2012 IEEE.

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U2 - 10.1109/CNNA.2012.6331450

DO - 10.1109/CNNA.2012.6331450

M3 - Conference contribution

SN - 9781467302890

BT - International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl.

T2 - 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012

Y2 - 1 July 2012

ER -

A compact FPGA implementation of a bit-serial SIMD cellular processor array

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