A compile-time partitioning strategy for non-rectangular loop nests

Rizos Sakellariou

doi:10.1109/IPPS.1997.580968

A compile-time partitioning strategy for non-rectangular loop nests

Rizos Sakellariou^*

^*Corresponding author for this work

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Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop. The minimization of load imbalance, on the basis of symbolic cost estimates, is considered the main objective; however, options which may increase other sources of overhead are avoided. Experimental results on a virtual shared memory computer are also presented.

Original language	English
Title of host publication	Proceedings 11th International Parallel Processing Symposium
Place of Publication	Los Alamitos, CA
Publisher	IEEE Computer Society
Pages	633-637
Number of pages	5
ISBN (Electronic)	0818677945
ISBN (Print)	0818677937, 0818677929
DOIs	https://doi.org/10.1109/IPPS.1997.580968
Publication status	Published - Apr 1997
Event	Proceedings of the 1997 11th International Parallel Processing Symposium, IPPS 97 - Geneva, Switz Duration: 1 Apr 1997 → 5 Apr 1997

Publication series

Name	Proceedings of the International Parallel Processing Symposium, IPPS
Publisher	IEEE Computer Society Press
ISSN (Print)	1063-7133

Conference

Conference	Proceedings of the 1997 11th International Parallel Processing Symposium, IPPS 97
City	Geneva, Switz
Period	1/04/97 → 5/04/97

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10.1109/IPPS.1997.580968

Cite this

@inproceedings{c1fae77815eb41fba13fde43656f8839,

title = "A compile-time partitioning strategy for non-rectangular loop nests",

abstract = "This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop. The minimization of load imbalance, on the basis of symbolic cost estimates, is considered the main objective; however, options which may increase other sources of overhead are avoided. Experimental results on a virtual shared memory computer are also presented.",

author = "Rizos Sakellariou",

year = "1997",

month = apr,

doi = "10.1109/IPPS.1997.580968",

language = "English",

isbn = "0818677937",

series = "Proceedings of the International Parallel Processing Symposium, IPPS",

publisher = "IEEE Computer Society ",

pages = "633--637",

booktitle = "Proceedings 11th International Parallel Processing Symposium",

address = "United States",

note = "Proceedings of the 1997 11th International Parallel Processing Symposium, IPPS 97 ; Conference date: 01-04-1997 Through 05-04-1997",

}

Sakellariou, R 1997, A compile-time partitioning strategy for non-rectangular loop nests. in Proceedings 11th International Parallel Processing Symposium. Proceedings of the International Parallel Processing Symposium, IPPS, IEEE Computer Society , Los Alamitos, CA, pp. 633-637, Proceedings of the 1997 11th International Parallel Processing Symposium, IPPS 97, Geneva, Switz, 1/04/97. https://doi.org/10.1109/IPPS.1997.580968

A compile-time partitioning strategy for non-rectangular loop nests. / Sakellariou, Rizos.
Proceedings 11th International Parallel Processing Symposium. Los Alamitos, CA: IEEE Computer Society , 1997. p. 633-637 (Proceedings of the International Parallel Processing Symposium, IPPS).

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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ER -

A compile-time partitioning strategy for non-rectangular loop nests

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