A GALS infrastructure for a massively parallel multiprocessor

Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang

Research output: Contribution to journalArticlepeer-review

Abstract

The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips. © 2007 IEEE.
Original languageEnglish
Pages (from-to)454-463
Number of pages9
JournalIEEE Design and Test of Computers
Volume24
Issue number5
DOIs
Publication statusPublished - Sept 2007

Keywords

  • Bandwidth
  • Fabrics
  • GALS
  • Magnetic cores
  • Massively parallel multiprocessor
  • Neural modeling
  • Protocols
  • Receivers
  • Self-timed interconnect
  • Spinnaker
  • Timing
  • Wires

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