A general-purpose CMOS vision chip with a processor-per-pixel SIMD array

P. Dudek; P. J. Hicks

A general-purpose CMOS vision chip with a processor-per-pixel SIMD array

P. Dudek, P. J. Hicks

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

The paper discusses the architecture and implementation of a new SIMD focal-plane processor array integrated circuit. The chip employs switched-current «analogue microprocessors» as processing nodes in a digital-like massively parallel computer architecture. Using analogue processing elements allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21×21 SCAMP vision chip is fabricated in a 0.6μm CMOS technology and achieves a cell size of 98.6μm×98.6μm. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and CNN-based processors. Experimental results are presented. © 2001 IEEE.

Original language	English
Title of host publication	European Solid-State Circuits Conference\|European Solid-State Circuits Conf.
Pages	213-216
Number of pages	3
Publication status	Published - 2001
Event	27th European Solid-State Circuits Conference, ESSCIRC 2001 - Villach Duration: 1 Jul 2001 → …

Conference

Conference	27th European Solid-State Circuits Conference, ESSCIRC 2001
City	Villach
Period	1/07/01 → …

Cite this

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title = "A general-purpose CMOS vision chip with a processor-per-pixel SIMD array",

abstract = "The paper discusses the architecture and implementation of a new SIMD focal-plane processor array integrated circuit. The chip employs switched-current «analogue microprocessors» as processing nodes in a digital-like massively parallel computer architecture. Using analogue processing elements allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21×21 SCAMP vision chip is fabricated in a 0.6μm CMOS technology and achieves a cell size of 98.6μm×98.6μm. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and CNN-based processors. Experimental results are presented. {\textcopyright} 2001 IEEE.",

author = "P. Dudek and Hicks, {P. J.}",

year = "2001",

language = "English",

pages = "213--216",

booktitle = "European Solid-State Circuits Conference|European Solid-State Circuits Conf.",

note = "27th European Solid-State Circuits Conference, ESSCIRC 2001 ; Conference date: 01-07-2001",

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TY - GEN

T1 - A general-purpose CMOS vision chip with a processor-per-pixel SIMD array

AU - Dudek, P.

AU - Hicks, P. J.

PY - 2001

Y1 - 2001

N2 - The paper discusses the architecture and implementation of a new SIMD focal-plane processor array integrated circuit. The chip employs switched-current «analogue microprocessors» as processing nodes in a digital-like massively parallel computer architecture. Using analogue processing elements allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21×21 SCAMP vision chip is fabricated in a 0.6μm CMOS technology and achieves a cell size of 98.6μm×98.6μm. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and CNN-based processors. Experimental results are presented. © 2001 IEEE.

AB - The paper discusses the architecture and implementation of a new SIMD focal-plane processor array integrated circuit. The chip employs switched-current «analogue microprocessors» as processing nodes in a digital-like massively parallel computer architecture. Using analogue processing elements allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21×21 SCAMP vision chip is fabricated in a 0.6μm CMOS technology and achieves a cell size of 98.6μm×98.6μm. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and CNN-based processors. Experimental results are presented. © 2001 IEEE.

M3 - Conference contribution

SP - 213

EP - 216

BT - European Solid-State Circuits Conference|European Solid-State Circuits Conf.

T2 - 27th European Solid-State Circuits Conference, ESSCIRC 2001

Y2 - 1 July 2001

ER -

A general-purpose CMOS vision chip with a processor-per-pixel SIMD array

Abstract

Conference

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