A general-purpose processor-per-pixel analog SIMD vision chip

Piotr Dudek; Peter J. Hicks

doi:10.1109/TCSI.2004.840093

A general-purpose processor-per-pixel analog SIMD vision chip

Research output: Contribution to journal › Article › peer-review

Abstract

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 × 21 vision chip is fabricated in a 0.6 μm CMOS technology and achieves a cell size of 98.6 μm × 98.6 μm. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper. © 2005 IEEE.

Original language	English
Pages (from-to)	13-20
Number of pages	7
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	52
Issue number	1
DOIs	https://doi.org/10.1109/TCSI.2004.840093
Publication status	Published - Jan 2005

Keywords

Analog processor array
CMOS imager
Smart sensor
Vision chip

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10.1109/TCSI.2004.840093

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abstract = "A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 × 21 vision chip is fabricated in a 0.6 μm CMOS technology and achieves a cell size of 98.6 μm × 98.6 μm. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper. {\textcopyright} 2005 IEEE.",

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AB - A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 × 21 vision chip is fabricated in a 0.6 μm CMOS technology and achieves a cell size of 98.6 μm × 98.6 μm. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper. © 2005 IEEE.

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KW - Smart sensor

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A general-purpose processor-per-pixel analog SIMD vision chip

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Keywords

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