A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array

Alexey Lopich; Piotr Dudek

doi:10.1109/CICC.2013.6658542

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications. © 2013 IEEE.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference, CICC 2013
Publisher	IEEE
ISBN (Print)	9781467361460
DOIs	https://doi.org/10.1109/CICC.2013.6658542
Publication status	Published - 7 Nov 2013
Event	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA Duration: 7 Nov 2013 → …

Conference

Conference	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
City	San Jose, CA
Period	7/11/13 → …

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10.1109/CICC.2013.6658542

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title = "A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array",

abstract = "In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications. {\textcopyright} 2013 IEEE.",

author = "Alexey Lopich and Piotr Dudek",

year = "2013",

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doi = "10.1109/CICC.2013.6658542",

language = "English",

isbn = "9781467361460",

booktitle = "Proceedings of the Custom Integrated Circuits Conference, CICC 2013",

publisher = "IEEE",

address = "United States",

note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 07-11-2013",

}

Lopich, A & Dudek, P 2013, A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. in Proceedings of the Custom Integrated Circuits Conference, CICC 2013. IEEE, 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, 7/11/13. https://doi.org/10.1109/CICC.2013.6658542

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N2 - In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications. © 2013 IEEE.

AB - In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications. © 2013 IEEE.

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DO - 10.1109/CICC.2013.6658542

M3 - Conference contribution

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PB - IEEE

T2 - 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013

Y2 - 7 November 2013

ER -

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array

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