A hardware implementation of multi-level threshold logic for artificial neural net

R. Neville

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach. © 2006 IEEE.
    Original languageEnglish
    Title of host publicationIEEE International Conference on Neural Networks - Conference Proceedings|IEEE Int. Conf. Neural. Netw. Conf. Proc.
    PublisherIEEE
    Pages2845-2851
    Number of pages6
    ISBN (Print)0780394909, 9780780394902
    DOIs
    Publication statusPublished - 2006
    EventInternational Joint Conference on Neural Networks 2006, IJCNN '06 - Vancouver, BC
    Duration: 1 Jul 2006 → …
    http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2006.html#Neville06http://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06

    Conference

    ConferenceInternational Joint Conference on Neural Networks 2006, IJCNN '06
    CityVancouver, BC
    Period1/07/06 → …
    Internet address

    Keywords

    • Hardware implementation
    • Multi-level
    • Neural functionality
    • Neural networks
    • Threshold logic

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