A hardware implementation of multi-level threshold logic for artificial neural net

R. Neville

doi:10.1109/IJCNN.2006.247213

A hardware implementation of multi-level threshold logic for artificial neural net

R. Neville

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach. © 2006 IEEE.

Original language	English
Title of host publication	IEEE International Conference on Neural Networks - Conference Proceedings\|IEEE Int. Conf. Neural. Netw. Conf. Proc.
Publisher	IEEE
Pages	2845-2851
Number of pages	6
ISBN (Print)	0780394909, 9780780394902
DOIs	https://doi.org/10.1109/IJCNN.2006.247213
Publication status	Published - 2006
Event	International Joint Conference on Neural Networks 2006, IJCNN '06 - Vancouver, BC Duration: 1 Jul 2006 → … http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2006.html#Neville06http://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06

Conference

Conference	International Joint Conference on Neural Networks 2006, IJCNN '06
City	Vancouver, BC
Period	1/07/06 → …
Internet address	http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2006.html#Neville06http://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06

Keywords

Hardware implementation
Multi-level
Neural functionality
Neural networks
Threshold logic

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10.1109/IJCNN.2006.247213

Cite this

@inproceedings{d149114c48f84ec099b96610deec2563,

title = "A hardware implementation of multi-level threshold logic for artificial neural net",

abstract = "The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach. {\textcopyright} 2006 IEEE.",

keywords = "Hardware implementation, Multi-level, Neural functionality, Neural networks, Threshold logic",

author = "R. Neville",

year = "2006",

doi = "10.1109/IJCNN.2006.247213",

language = "English",

isbn = "0780394909",

pages = "2845--2851",

booktitle = "IEEE International Conference on Neural Networks - Conference Proceedings|IEEE Int. Conf. Neural. Netw. Conf. Proc.",

publisher = "IEEE",

address = "United States",

note = "International Joint Conference on Neural Networks 2006, IJCNN '06 ; Conference date: 01-07-2006",

url = "http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2006.html#Neville06http://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ijcnn/Neville06",

}

Neville, R 2006, A hardware implementation of multi-level threshold logic for artificial neural net. in IEEE International Conference on Neural Networks - Conference Proceedings|IEEE Int. Conf. Neural. Netw. Conf. Proc.. IEEE, pp. 2845-2851, International Joint Conference on Neural Networks 2006, IJCNN '06, Vancouver, BC, 1/07/06. https://doi.org/10.1109/IJCNN.2006.247213

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PY - 2006

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N2 - The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach. © 2006 IEEE.

AB - The need to implement neural structures is paramount, and a more device-centric view leads to an understanding of the scope of performance enhancements that can be achieved. A sequence of empirical investigations and their rationale are described, in which different types of simple junction-based devices perform multi-level threshold logic functions that are required for neural systems. This enables connectionists to comprehend the types of building blocks that can be used to implement connectionist systems. The paper focuses on early results: some of the aims have been demonstrated and amplified through empirical implementations, making it possible to assess the strength and weakness of the approach. © 2006 IEEE.

KW - Hardware implementation

KW - Multi-level

KW - Neural functionality

KW - Neural networks

KW - Threshold logic

U2 - 10.1109/IJCNN.2006.247213

DO - 10.1109/IJCNN.2006.247213

M3 - Conference contribution

SN - 0780394909

SN - 9780780394902

SP - 2845

EP - 2851

BT - IEEE International Conference on Neural Networks - Conference Proceedings|IEEE Int. Conf. Neural. Netw. Conf. Proc.

PB - IEEE

T2 - International Joint Conference on Neural Networks 2006, IJCNN '06

Y2 - 1 July 2006

ER -

A hardware implementation of multi-level threshold logic for artificial neural net

Abstract

Conference

Keywords

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