A High-Resolution CMOS Time to Digital Converter Utilising a Vernier Delay Line

P Dudek, S Szczepanski, J V Hatfield

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	240-247
Number of pages	8
Journal	IEEE Journal of Solid State Circuits
Volume	35
Issue number	2
Publication status	Published - Feb 2000

Cite this

@article{37bc1c65c0714e42abe514716d760828,

title = "A High-Resolution CMOS Time to Digital Converter Utilising a Vernier Delay Line",

author = "P Dudek and S Szczepanski and Hatfield, \{J V\}",

year = "2000",

month = feb,

language = "English",

volume = "35",

pages = "240--247",

journal = "IEEE Journal of Solid State Circuits",

publisher = "IEEE",

number = "2",

}