A low latency wormhole router for asynchronous on-chip networks

Wei Song; Doug Edwards

doi:10.1109/ASPDAC.2010.5419841

A low latency wormhole router for asynchronous on-chip networks

Wei Song, Doug Edwards

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous worm-hole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 μm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port.

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC\|Proc Asia South Pac Des Autom Conf
Place of Publication	USA
Publisher	IEEE
Pages	437-443
Number of pages	6
ISBN (Print)	9781424457656
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419841
Publication status	Published - 2010
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei Duration: 1 Jul 2010 → …

Conference

Conference	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
City	Taipei
Period	1/07/10 → …

Keywords

network-on-chip

Access to Document

10.1109/ASPDAC.2010.5419841

Cite this

@inproceedings{0a7dcdc80f0342e09d3da5ee3ef5b94b,

title = "A low latency wormhole router for asynchronous on-chip networks",

abstract = "Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous worm-hole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 μm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port.",

keywords = "network-on-chip",

author = "Wei Song and Doug Edwards",

year = "2010",

doi = "10.1109/ASPDAC.2010.5419841",

language = "English",

isbn = "9781424457656",

pages = "437--443",

booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|Proc Asia South Pac Des Autom Conf",

publisher = "IEEE",

address = "United States",

note = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 01-07-2010",

}

Song, W & Edwards, D 2010, A low latency wormhole router for asynchronous on-chip networks. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|Proc Asia South Pac Des Autom Conf. IEEE, USA, pp. 437-443, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, 1/07/10. https://doi.org/10.1109/ASPDAC.2010.5419841

TY - GEN

T1 - A low latency wormhole router for asynchronous on-chip networks

AU - Song, Wei

AU - Edwards, Doug

PY - 2010

Y1 - 2010

N2 - Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous worm-hole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 μm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port.

AB - Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous worm-hole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 μm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port.

KW - network-on-chip

U2 - 10.1109/ASPDAC.2010.5419841

DO - 10.1109/ASPDAC.2010.5419841

M3 - Conference contribution

SN - 9781424457656

SP - 437

EP - 443

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|Proc Asia South Pac Des Autom Conf

PB - IEEE

CY - USA

T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

Y2 - 1 July 2010

ER -

A low latency wormhole router for asynchronous on-chip networks

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this