A novel programmable parallel CRC circuit

Martin Grymel; Steve B. Furber

doi:10.1109/TVLSI.2010.2058872

A novel programmable parallel CRC circuit

Martin Grymel, Steve B. Furber

Advanced Processor Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A new hardware scheme for computing the transition and control matrix of a parallel cyclic redundancy checksum is proposed. This opens possibilities for parallel high-speed cyclic redundancy checksum circuits that reconfigure very rapidly to new polynomials. The area requirements are lower than those for a realization storing a precomputed matrix. An additional simplification arises as only the polynomial needs to be supplied. The derived equations allow the width of the data to be processed in parallel to be selected independently of the degree of the polynomial. The new design has been simulated and outperforms a recently proposed architecture significantly in speed, area, and energy efficiency. © 2010 IEEE.

Original language	English
Article number	5549980
Pages (from-to)	1898-1902
Number of pages	4
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	10
DOIs	https://doi.org/10.1109/TVLSI.2010.2058872
Publication status	Published - Oct 2011

Keywords

Cyclic redundancy checksum (CRC)
digital logic
error detection
parallel
programmable

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10.1109/TVLSI.2010.2058872

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A novel programmable parallel CRC circuit

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Keywords

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