A partial reconfiguration controller for Altera Stratix V FPGAs

Zhenzhong Xiao, Dirk Koch, Mikel Lujan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


With the introduction of the Stratix V family, the FPGA vendor Altera is now fully supporting partial reconfiguration in all their recent FPGA devices.
A distinct feature in the Altera architecture is that reconfigurable regions can be arbitrarily defined which is possible by writing a configuration mask prior to writing the actual configuration data to the FPGA fabric.

In this paper, we will present details and the flow for implementing partial reconfiguration using Altera FPGAs, as well as a study on configuration bitstream sizes and configuration speeds for various resource and bounding-box aspect ratio variants. The results are used to build a partial reconfiguration controller that is featuring a lightweight but effective bitstream decompression module for greatly improving configuration speed on a DE5-net board.
Original languageEnglish
Title of host publication26th International Conference on Field Programmable Logic and Applications (FPL)
Subtitle of host publicationFPL 2016
PublisherIEEE Computer Society
Number of pages4
ISBN (Electronic)1946-1488
Publication statusPublished - 29 Aug 2016


  • FPGA
  • Partial Reconfiguration


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