A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

Piotr Dudek, Alexey Lopich, Viktor Gruev

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32x32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMD mode, and processes the image data acquired by the top-layer backside illuminated photosensor circuit. The intra-processor inter-layer communication is achieved by means of throughsilicon vias, and the system is partitioned to minimise the area overhead associated with this communication. The processor comprises 4 analogue and 12 binary registers, and supports arithmetic and logic operations. Various sensor structures have been implemented to evaluate the efficiency of photo-sensing in SOI technology. The prototype circuit measures 2mmx2mm, with 30μmx30μm pixel pitch. The architecture and circuit design issues are presented in the paper. ©2009 IEEE.
    Original languageEnglish
    Title of host publicationECCTD 2009 - European Conference on Circuit Theory and Design Conference Program|ECCTD - Eur. Conf. Circuit Theory Des. Conf. Program
    Pages193-196
    Number of pages3
    DOIs
    Publication statusPublished - 2009
    EventECCTD 2009 - European Conference on Circuit Theory and Design Conference Program - Antalya
    Duration: 1 Jul 2009 → …

    Conference

    ConferenceECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
    CityAntalya
    Period1/07/09 → …

    Fingerprint

    Dive into the research topics of 'A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology'. Together they form a unique fingerprint.

    Cite this