Abstract
This paper presents a new processing cell circuit, suitable for use in massively parallel fine-grain processor arrays, oriented towards image processing applications. The design, based on dynamic logic, is efficient for both local and global operations. In this paper we discuss design trade-offs and provide detailed description of the architecture. A cellular processor array based on the presented design can operate in both discrete- and continuous-time domains. Asynchronous execution of global operations significantly increases overall performance. Simulation results indicate the performance in the range from 1.1 (unsigned products) to 2900 (asynchronous binary processing) MOPS/cell.
| Original language | English |
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| Title of host publication | Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006|Proc. Fourth Int. Conf. Circ. Signals Syst. |
| Pages | 296-301 |
| Number of pages | 5 |
| Publication status | Published - 2006 |
| Event | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 - San Francisco, CA Duration: 1 Jul 2006 → … |
Conference
| Conference | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 |
|---|---|
| City | San Francisco, CA |
| Period | 1/07/06 → … |
Keywords
- Asynchronous processing
- Cellular processor arrays
- SIMD arrays
- Vision chips
- Wave propagations