A processor element for a mixed signal cellular processor array vision chip

Stephen J. Carey; Alexey Lopich; Piotr Dudek

doi:10.1109/ISCAS.2011.5937875

A processor element for a mixed signal cellular processor array vision chip

Stephen J. Carey, Alexey Lopich, Piotr Dudek

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in 0.18m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also available. The processing element has dimensions of 3232m and is designed to operate at 10MHz. A test chip has been fabricated. © 2011 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems\|Proc IEEE Int Symp Circuits Syst
Pages	1564-1567
Number of pages	3
DOIs	https://doi.org/10.1109/ISCAS.2011.5937875
Publication status	Published - 2011
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro Duration: 1 Jul 2011 → … http://dx.doi.org/10.1109/ISCAS.2011.5937774

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
City	Rio de Janeiro
Period	1/07/11 → …
Internet address	http://dx.doi.org/10.1109/ISCAS.2011.5937774

Keywords

CMOS integrated circuits
Digital circuits
Digital signal processors
Parallel processing systems
Pixels

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10.1109/ISCAS.2011.5937875

Cite this

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title = "A processor element for a mixed signal cellular processor array vision chip",

abstract = "A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in 0.18m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also available. The processing element has dimensions of 3232m and is designed to operate at 10MHz. A test chip has been fabricated. {\textcopyright} 2011 IEEE.",

keywords = "CMOS integrated circuits, Digital circuits, Digital signal processors, Parallel processing systems, Pixels",

author = "Carey, {Stephen J.} and Alexey Lopich and Piotr Dudek",

note = "Analogue domain;Cellular Processor Array;CMOS technology;Digital domain;Digital memory;Mixed signal;Processing capability;Processing elements;Processor element;Test chips;Vision chips;; 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 01-07-2011",

year = "2011",

doi = "10.1109/ISCAS.2011.5937875",

language = "English",

isbn = "9781424494736",

pages = "1564--1567",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst",

url = "http://dx.doi.org/10.1109/ISCAS.2011.5937774",

}

Carey, SJ, Lopich, A & Dudek, P 2011, A processor element for a mixed signal cellular processor array vision chip. in Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst. pp. 1564-1567, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, 1/07/11. https://doi.org/10.1109/ISCAS.2011.5937875

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T1 - A processor element for a mixed signal cellular processor array vision chip

AU - Carey, Stephen J.

AU - Lopich, Alexey

AU - Dudek, Piotr

N1 - Analogue domain;Cellular Processor Array;CMOS technology;Digital domain;Digital memory;Mixed signal;Processing capability;Processing elements;Processor element;Test chips;Vision chips;

PY - 2011

Y1 - 2011

N2 - A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in 0.18m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also available. The processing element has dimensions of 3232m and is designed to operate at 10MHz. A test chip has been fabricated. © 2011 IEEE.

AB - A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in 0.18m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also available. The processing element has dimensions of 3232m and is designed to operate at 10MHz. A test chip has been fabricated. © 2011 IEEE.

KW - CMOS integrated circuits

KW - Digital circuits

KW - Digital signal processors

KW - Parallel processing systems

KW - Pixels

U2 - 10.1109/ISCAS.2011.5937875

DO - 10.1109/ISCAS.2011.5937875

M3 - Conference contribution

SN - 9781424494736

SP - 1564

EP - 1567

BT - Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst

T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

Y2 - 1 July 2011

ER -

A processor element for a mixed signal cellular processor array vision chip

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Keywords

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