A RISC hardware platform for low power java

Paul Capewell; Ian Watson

doi:10.1109/ICVD.2005.33

A RISC hardware platform for low power java

Paul Capewell, Ian Watson

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of resources available in many embedded systems. Hardware support for Java is a potential solution, reducing memory and power requirements while increasing execution speed. This paper presents a prototype architecture for hardware Java support within a RISC processor core, along with a synthesised asynchronous implementation. A breakdown of gate and silicon level simulation results quantifies where performance increases are achieved, providing a template for future work. © 2005 IEEE.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on VLSI Design\|Proc IEEE Int Conf VLSI Des
Publisher	IEEE
Pages	138-143
Number of pages	5
ISBN (Print)	0769522645
DOIs	https://doi.org/10.1109/ICVD.2005.33
Publication status	Published - 2005
Event	18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata Duration: 1 Jul 2005 → … http://intranet.cs.man.ac.uk/apt/publications/papers/cb_vlsides_05.php

Conference

Conference	18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
City	Kolkata
Period	1/07/05 → …
Internet address	http://intranet.cs.man.ac.uk/apt/publications/papers/cb_vlsides_05.php

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10.1109/ICVD.2005.33

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title = "A RISC hardware platform for low power java",

abstract = "Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of resources available in many embedded systems. Hardware support for Java is a potential solution, reducing memory and power requirements while increasing execution speed. This paper presents a prototype architecture for hardware Java support within a RISC processor core, along with a synthesised asynchronous implementation. A breakdown of gate and silicon level simulation results quantifies where performance increases are achieved, providing a template for future work. {\textcopyright} 2005 IEEE.",

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AB - Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of resources available in many embedded systems. Hardware support for Java is a potential solution, reducing memory and power requirements while increasing execution speed. This paper presents a prototype architecture for hardware Java support within a RISC processor core, along with a synthesised asynchronous implementation. A breakdown of gate and silicon level simulation results quantifies where performance increases are achieved, providing a template for future work. © 2005 IEEE.

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BT - Proceedings of the IEEE International Conference on VLSI Design|Proc IEEE Int Conf VLSI Des

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T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems

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A RISC hardware platform for low power java

Abstract

Conference

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