A Security Library for FPGA Interlays

Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Many CPU design houses have added dedicated
support for cryptography in recent processor generations, in-
cluding Intel, IBM, and ARM. While adding accelerators and/or
dedicated instructions boosts performance on cryptography, we
are investigating a different approach that is not adding extra
silicon area: We study to replace the hardened NEON SIMD unit
of an ARM Cortex-A9 with an identical sized FPGA fabric, called
an interlay. This will be used for implementing cryptographic
instructions in soft-logic. We show that this approach can
outperform the hardened NEON by up to 7.7× on AES and
provide functionality that is not available in the hardened ARM.
Original languageEnglish
Title of host publicationInternational Conference on Field Programmable Logic and Applications (FPL)
Place of PublicationGhent, Belgium
ISBN (Electronic)978-9-0903-0428-1
ISBN (Print)978-1-5386-2040-3
Publication statusPublished - 5 Oct 2017


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