A SIMD cellular processor array vision chip with asynchronous processing capabilities

Alexey Lopich, Piotr Dudek

    Research output: Contribution to journalArticlepeer-review


    This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 × 22 proof-of-concept array has been manufactured in 0.35 μm CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low-and medium-level image processing on the chip are presented. © 2011 IEEE.
    Original languageEnglish
    Article number5754622
    Pages (from-to)2420-2431
    Number of pages11
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Issue number10
    Publication statusPublished - 2011


    • Asynchronous image processing
    • cellular processor array
    • smart sensor
    • vision chip


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