Abstract
FPGA implementation is essential for verifying asynchronous NoCs and validating design requirements. However, prototyping these circuits presents challenges in preserving timing integrity due to mismatches with FPGA timing models. The adoption of bundled-data NoCs with one-sided relative timing
constraints further complicates their high-performance mapping. Current CAD flows focus on correctness, but performance optimization is hindered by poor control over timing convergence, leading to overdesigned margins and wasted performance. This paper proposes a methodology that tightly controls relative timing margins through selective net rerouting and delay constraint tuning. On an Artix-7 FPGA using Vivado, the implemented asynchronous NoC switch achieves 40% lower latency and up to 75% lower energy-per-packet than a synchronous counterpart.
constraints further complicates their high-performance mapping. Current CAD flows focus on correctness, but performance optimization is hindered by poor control over timing convergence, leading to overdesigned margins and wasted performance. This paper proposes a methodology that tightly controls relative timing margins through selective net rerouting and delay constraint tuning. On an Artix-7 FPGA using Vivado, the implemented asynchronous NoC switch achieves 40% lower latency and up to 75% lower energy-per-packet than a synchronous counterpart.
| Original language | English |
|---|---|
| Title of host publication | IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) |
| Publisher | IEEE |
| Publication status | Accepted/In press - 10 Mar 2025 |
Keywords
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- formatting
- style
- stylist
- insert