Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study

Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim Garside, Mikel Luján

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    Architectural simulation is a fundamental tool for modern computing system design. Computer architects can choose from a large set of software simulators that provide a robust and efficient platform for design exploration although, if the new architecture incorporates unconventional or novel features not supported by the existing simulators, the designers must develop their own. As reconfigurable hardware platforms grow more computationally capable we observe a move from software simulators towards these hardware platforms. The introduction of high-level HDLs, such as Blue spec System Verilog (BSV), offers improved productivity while still providing a tool flow capable of exploiting reconfigurable platforms. This paper focuses on understanding how to accelerate the simulation of the interconnection network of SpiNNaker [1], a massively-parallel computer for neural simulation. We analysed the modelling choices and trade-offs made during the implementation of the software (SW) model as well as those made when developing a new hardware model (HW) built on a Xilinx FPGA.
    Original languageEnglish
    Title of host publicationField-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
    Place of PublicationUSA
    PublisherIEEE
    Pages96-96
    Number of pages1
    DOIs
    Publication statusPublished - 3 May 2015
    EventField-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on - Vancouver BC
    Duration: 3 May 20155 May 2015

    Conference

    ConferenceField-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
    CityVancouver BC
    Period3/05/155/05/15

    Keywords

    • digital simulation;field programmable gate arrays;hardware description languages;interconnections;logic design;reconfigurable architectures;software architecture;BSV;Blue spec system Verilog;FPGA SpiNNaker;HW model;SW model;Xilinx FPGA;accelerating interconnect analysis;architectural simulation;computer architecture;computing system design;design exploration;hardware model;high-level HDLs;interconnection network;massively-parallel computer;neural simulation;reconfigurable hardware platforms;software model;software simulators;Accuracy;Analytical models;Computational modeling;Field programmable gate arrays;Hardware;Load modeling;Software

    Fingerprint

    Dive into the research topics of 'Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study'. Together they form a unique fingerprint.

    Cite this