Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study

Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim Garside; Mikel Luján

doi:10.1109/FCCM.2015.47

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study

Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim Garside, Mikel Luján

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Architectural simulation is a fundamental tool for modern computing system design. Computer architects can choose from a large set of software simulators that provide a robust and efficient platform for design exploration although, if the new architecture incorporates unconventional or novel features not supported by the existing simulators, the designers must develop their own. As reconfigurable hardware platforms grow more computationally capable we observe a move from software simulators towards these hardware platforms. The introduction of high-level HDLs, such as Blue spec System Verilog (BSV), offers improved productivity while still providing a tool flow capable of exploiting reconfigurable platforms. This paper focuses on understanding how to accelerate the simulation of the interconnection network of SpiNNaker [1], a massively-parallel computer for neural simulation. We analysed the modelling choices and trade-offs made during the implementation of the software (SW) model as well as those made when developing a new hardware model (HW) built on a Xilinx FPGA.

Original language	English
Title of host publication	Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
Place of Publication	USA
Publisher	IEEE
Pages	96-96
Number of pages	1
DOIs	https://doi.org/10.1109/FCCM.2015.47
Publication status	Published - 3 May 2015
Event	Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on - Vancouver BC Duration: 3 May 2015 → 5 May 2015

Conference

Conference	Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
City	Vancouver BC
Period	3/05/15 → 5/05/15

Keywords

digital simulation;field programmable gate arrays;hardware description languages;interconnections;logic design;reconfigurable architectures;software architecture;BSV;Blue spec system Verilog;FPGA SpiNNaker;HW model;SW model;Xilinx FPGA;accelerating interconnect analysis;architectural simulation;computer architecture;computing system design;design exploration;hardware model;high-level HDLs;interconnection network;massively-parallel computer;neural simulation;reconfigurable hardware platforms;software model;software simulators;Accuracy;Analytical models;Computational modeling;Field programmable gate arrays;Hardware;Load modeling;Software

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10.1109/FCCM.2015.47

Cite this

@inproceedings{94de26003a2248e38a652be1c711f7be,

title = "Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study",

abstract = "Architectural simulation is a fundamental tool for modern computing system design. Computer architects can choose from a large set of software simulators that provide a robust and efficient platform for design exploration although, if the new architecture incorporates unconventional or novel features not supported by the existing simulators, the designers must develop their own. As reconfigurable hardware platforms grow more computationally capable we observe a move from software simulators towards these hardware platforms. The introduction of high-level HDLs, such as Blue spec System Verilog (BSV), offers improved productivity while still providing a tool flow capable of exploiting reconfigurable platforms. This paper focuses on understanding how to accelerate the simulation of the interconnection network of SpiNNaker [1], a massively-parallel computer for neural simulation. We analysed the modelling choices and trade-offs made during the implementation of the software (SW) model as well as those made when developing a new hardware model (HW) built on a Xilinx FPGA.",

keywords = "digital simulation;field programmable gate arrays;hardware description languages;interconnections;logic design;reconfigurable architectures;software architecture;BSV;Blue spec system Verilog;FPGA SpiNNaker;HW model;SW model;Xilinx FPGA;accelerating interconnect analysis;architectural simulation;computer architecture;computing system design;design exploration;hardware model;high-level HDLs;interconnection network;massively-parallel computer;neural simulation;reconfigurable hardware platforms;software model;software simulators;Accuracy;Analytical models;Computational modeling;Field programmable gate arrays;Hardware;Load modeling;Software",

author = "Mohsen Ghasempour and Jonathan Heathcote and Javier Navaridas and Plana, {Luis A.} and Jim Garside and Mikel Luj{\'a}n",

year = "2015",

month = may,

day = "3",

doi = "10.1109/FCCM.2015.47",

language = "English",

pages = "96--96",

booktitle = "Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on",

publisher = "IEEE",

address = "United States",

note = "Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on ; Conference date: 03-05-2015 Through 05-05-2015",

}

Ghasempour, M, Heathcote, J, Navaridas, J, Plana, LA, Garside, J & Luján, M 2015, Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. in Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on. IEEE, USA, pp. 96-96, Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, Vancouver BC, 3/05/15. https://doi.org/10.1109/FCCM.2015.47

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. / Ghasempour, Mohsen; Heathcote, Jonathan; Navaridas, Javier et al.
Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on. USA: IEEE, 2015. p. 96-96.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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AU - Garside, Jim

AU - Luján, Mikel

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N2 - Architectural simulation is a fundamental tool for modern computing system design. Computer architects can choose from a large set of software simulators that provide a robust and efficient platform for design exploration although, if the new architecture incorporates unconventional or novel features not supported by the existing simulators, the designers must develop their own. As reconfigurable hardware platforms grow more computationally capable we observe a move from software simulators towards these hardware platforms. The introduction of high-level HDLs, such as Blue spec System Verilog (BSV), offers improved productivity while still providing a tool flow capable of exploiting reconfigurable platforms. This paper focuses on understanding how to accelerate the simulation of the interconnection network of SpiNNaker [1], a massively-parallel computer for neural simulation. We analysed the modelling choices and trade-offs made during the implementation of the software (SW) model as well as those made when developing a new hardware model (HW) built on a Xilinx FPGA.

AB - Architectural simulation is a fundamental tool for modern computing system design. Computer architects can choose from a large set of software simulators that provide a robust and efficient platform for design exploration although, if the new architecture incorporates unconventional or novel features not supported by the existing simulators, the designers must develop their own. As reconfigurable hardware platforms grow more computationally capable we observe a move from software simulators towards these hardware platforms. The introduction of high-level HDLs, such as Blue spec System Verilog (BSV), offers improved productivity while still providing a tool flow capable of exploiting reconfigurable platforms. This paper focuses on understanding how to accelerate the simulation of the interconnection network of SpiNNaker [1], a massively-parallel computer for neural simulation. We analysed the modelling choices and trade-offs made during the implementation of the software (SW) model as well as those made when developing a new hardware model (HW) built on a Xilinx FPGA.

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ER -

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study

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