Accurate cache and TLB characterization using hardware counters

Jack Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You

    Research output: Chapter in Book/Conference proceedingConference contribution

    Abstract

    We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions. © Springer-Verlag 2004.
    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.
    PublisherSpringer Nature
    Pages432-439
    Number of pages7
    Volume3038
    Publication statusPublished - 2004
    EventComputational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III -
    Duration: 1 Jan 1824 → …
    http://dblp.uni-trier.de/db/conf/iccS/iccS2004-3.html#DongarraMMSY04http://dblp.uni-trier.de/rec/bibtex/conf/iccS/DongarraMMSY04.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/iccS/DongarraMMSY04

    Publication series

    NameLecture Notes in Computer Science

    Conference

    ConferenceComputational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III
    Period1/01/24 → …
    Internet address

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