Adaptive pipeline depth control for processor power-management

Aristides Efthymiou; Jim D. Garside

doi:10.1109/ICCD.2002.1106812

Adaptive pipeline depth control for processor power-management

Aristides Efthymiou, Jim D. Garside

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors\|Proc IEEE Int Conf Comput Des VLSI Comput Process
Pages	454-457
Number of pages	3
DOIs	https://doi.org/10.1109/ICCD.2002.1106812
Publication status	Published - 2002
Event	International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg Duration: 1 Jul 2002 → … http://intranet.cs.man.ac.uk/apt/publications/papers/ICCD02.php

Conference

Conference	International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors
City	Freiburg
Period	1/07/02 → …
Internet address	http://intranet.cs.man.ac.uk/apt/publications/papers/ICCD02.php

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10.1109/ICCD.2002.1106812

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title = "Adaptive pipeline depth control for processor power-management",

abstract = "A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.",

author = "Aristides Efthymiou and Garside, {Jim D.}",

year = "2002",

doi = "10.1109/ICCD.2002.1106812",

language = "English",

pages = "454--457",

booktitle = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|Proc IEEE Int Conf Comput Des VLSI Comput Process",

note = "International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors ; Conference date: 01-07-2002",

url = "http://intranet.cs.man.ac.uk/apt/publications/papers/ICCD02.php",

}

Efthymiou, A & Garside, JD 2002, Adaptive pipeline depth control for processor power-management. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|Proc IEEE Int Conf Comput Des VLSI Comput Process. pp. 454-457, International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors, Freiburg, 1/07/02. https://doi.org/10.1109/ICCD.2002.1106812

TY - GEN

T1 - Adaptive pipeline depth control for processor power-management

AU - Efthymiou, Aristides

AU - Garside, Jim D.

PY - 2002

Y1 - 2002

N2 - A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

AB - A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.

U2 - 10.1109/ICCD.2002.1106812

DO - 10.1109/ICCD.2002.1106812

M3 - Conference contribution

SP - 454

EP - 457

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|Proc IEEE Int Conf Comput Des VLSI Comput Process

T2 - International Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors

Y2 - 1 July 2002

ER -

Adaptive pipeline depth control for processor power-management

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Conference

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