Abstract
In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMP-3 vision chip, comprising 128×128 array, fabricated in a 0.35μm CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed. © 2006 IEEE.
Original language | English |
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Title of host publication | CAMPS 2006 - International Workshop on Computer Architecture for Machine Perception and Sensing, Conference Proceedings|CAMPS - Int. Workshop Comput. Archit. Mach. Percept. Sens., Conf. Proc. |
Pages | 1-6 |
Number of pages | 5 |
DOIs | |
Publication status | Published - 2006 |
Event | CAMPS 2006 - International Workshop on Computer Architecture for Machine Perception and Sensing - Montreal, QC Duration: 1 Jul 2006 → … |
Conference
Conference | CAMPS 2006 - International Workshop on Computer Architecture for Machine Perception and Sensing |
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City | Montreal, QC |
Period | 1/07/06 → … |