Adaptive Word Reordering for Low-Power Inter-Chip Communication

Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasileios Pavlidis

Research output: Contribution to conferencePosterpeer-review

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The energy for data transfer has an increasing
effect on the total system energy as technology scales, often
overtaking computation energy. To reduce the power of interchip
interconnects, an adaptive encoding scheme called Adaptive
Word Reordering (AWR) is proposed that effectively decreases
the number of signal transitions, leading to a significant power
reduction. AWR outperforms other adaptive encoding schemes
in terms of decrease in transitions, yielding up to 73% reduction
in switching. Furthermore, complex bit transition computations
are represented as delays in the time domain to limit the
power overhead due to encoding. The saved power outweighs the
overhead beyond a moderate wire length where the I/O voltage
is assumed equal to the core voltage. For a typical I/O voltage,
the decrease in power is significant reaching 23% at just 1 mm.
Original languageEnglish
Publication statusAccepted/In press - 8 Nov 2018
EventDesign, Automation and Test in Europe - Florence, Italy
Duration: 25 Mar 201929 Nov 2019


ConferenceDesign, Automation and Test in Europe
Abbreviated titleDATE
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