Adding testability to an asynchronous interconnect for GALS SoC

Aristides Efthymiou, John Bainbridge, Douglas A. Edwards

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used as an example. Test patterns are generated by a custom program automatically, given the topology of the interconnect. In comparison to standard, asynchronous, full-scan LSSD methods, area savings in the order of 50% are noted.
    Original languageEnglish
    Title of host publicationProceedings of the Asian Test Symposium|Proc Asian Test Symp
    PublisherIEEE Computer Society
    Number of pages3
    Publication statusPublished - 2004
    EventProceedings of the Asian Test Symposium, ATS'04 - Kenting
    Duration: 1 Jul 2004 → …


    ConferenceProceedings of the Asian Test Symposium, ATS'04
    Period1/07/04 → …
    Internet address


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