Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware

X. Jin; M. Luján; M. M. Khan; Luis A. Plana; A. D. Rast; S. R. Welbourne; S. B. Furber

doi:10.1109/ISPDC.2010.10

Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware

X. Jin, M. Luján, M. M. Khan, Luis A. Plana, A. D. Rast, S. R. Welbourne, S. B. Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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Abstract

This paper demonstrates the feasibility and evaluates the performance of using the SpiNNaker neuromorphic hardware to simulate traditional non-spiking multi-layer per-ceptron networks with the backpropagation learning rule. In addition to investigating the mapping of checker-boarding partitioning scheme onto SpiNNaker, we propose a new algorithm called pipelined checker-boarding partitioning which introduces a pipelined mode and captures the parallelism within each partition of the weight matrix, allowing the overlapping of communication and computation. Not only does the proposed algorithm localize communication, but it can also hide a part of or even all the communication. The performance is evaluated with SpiNNaker configurations up to 1000 nodes (20000 cores). © 2010 IEEE.

Original language	English
Title of host publication	9th International Symposium on Parallel and Distributed Computing, ISPDC 2010\|Int. Symp. Parallel Distrib. Comput., ISPDC
Place of Publication	USA
Publisher	IEEE
Pages	9-16
Number of pages	7
ISBN (Print)	9780769541204
DOIs	https://doi.org/10.1109/ISPDC.2010.10
Publication status	Published - 2010
Event	9th International Symposium on Parallel and Distributed Computing, ISPDC 2010 - Istanbul Duration: 1 Jul 2010 → …

Conference

Conference	9th International Symposium on Parallel and Distributed Computing, ISPDC 2010
City	Istanbul
Period	1/07/10 → …

Keywords

Backpropagation
Mapping
Parallel
Perceptron
SpiNNaker

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Jin, X., Luján, M., Khan, M. M., Plana, L. A., Rast, A. D., Welbourne, S. R., & Furber, S. B. (2010). Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware. In 9th International Symposium on Parallel and Distributed Computing, ISPDC 2010|Int. Symp. Parallel Distrib. Comput., ISPDC (pp. 9-16). IEEE. https://doi.org/10.1109/ISPDC.2010.10

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title = "Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware",

abstract = "This paper demonstrates the feasibility and evaluates the performance of using the SpiNNaker neuromorphic hardware to simulate traditional non-spiking multi-layer per-ceptron networks with the backpropagation learning rule. In addition to investigating the mapping of checker-boarding partitioning scheme onto SpiNNaker, we propose a new algorithm called pipelined checker-boarding partitioning which introduces a pipelined mode and captures the parallelism within each partition of the weight matrix, allowing the overlapping of communication and computation. Not only does the proposed algorithm localize communication, but it can also hide a part of or even all the communication. The performance is evaluated with SpiNNaker configurations up to 1000 nodes (20000 cores). {\textcopyright} 2010 IEEE.",

keywords = "Backpropagation, Mapping, Parallel, Perceptron, SpiNNaker",

author = "X. Jin and M. Luj{\'a}n and Khan, {M. M.} and Plana, {Luis A.} and Rast, {A. D.} and Welbourne, {S. R.} and Furber, {S. B.}",

year = "2010",

doi = "10.1109/ISPDC.2010.10",

language = "English",

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pages = "9--16",

booktitle = "9th International Symposium on Parallel and Distributed Computing, ISPDC 2010|Int. Symp. Parallel Distrib. Comput., ISPDC",

publisher = "IEEE",

address = "United States",

note = "9th International Symposium on Parallel and Distributed Computing, ISPDC 2010 ; Conference date: 01-07-2010",

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Jin, X, Luján, M, Khan, MM, Plana, LA, Rast, AD, Welbourne, SR & Furber, SB 2010, Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware. in 9th International Symposium on Parallel and Distributed Computing, ISPDC 2010|Int. Symp. Parallel Distrib. Comput., ISPDC. IEEE, USA, pp. 9-16, 9th International Symposium on Parallel and Distributed Computing, ISPDC 2010, Istanbul, 1/07/10. https://doi.org/10.1109/ISPDC.2010.10

Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware. / Jin, X.; Luján, M.; Khan, M. M. et al.
9th International Symposium on Parallel and Distributed Computing, ISPDC 2010|Int. Symp. Parallel Distrib. Comput., ISPDC. USA: IEEE, 2010. p. 9-16.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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AU - Jin, X.

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AU - Welbourne, S. R.

AU - Furber, S. B.

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N2 - This paper demonstrates the feasibility and evaluates the performance of using the SpiNNaker neuromorphic hardware to simulate traditional non-spiking multi-layer per-ceptron networks with the backpropagation learning rule. In addition to investigating the mapping of checker-boarding partitioning scheme onto SpiNNaker, we propose a new algorithm called pipelined checker-boarding partitioning which introduces a pipelined mode and captures the parallelism within each partition of the weight matrix, allowing the overlapping of communication and computation. Not only does the proposed algorithm localize communication, but it can also hide a part of or even all the communication. The performance is evaluated with SpiNNaker configurations up to 1000 nodes (20000 cores). © 2010 IEEE.

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Algorithm for mapping multilayer BP networks onto the SpiNNaker neuromorphic hardware

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Keywords

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