AMULET3 revealed

J. D. Garside; S. B. Furber; S. H. Chung

doi:10.1109/ASYNC.1999.761522

AMULET3 revealed

J. D. Garside, S. B. Furber, S. H. Chung

Advanced Processor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Han'ard architecture to increase memory bandwidth and the inclusion of a reorder buffer to handle data forwarding and memory faults. © 1999 IEEE.

Original language	English
Title of host publication	Proceedings - International Symposium on Asynchronous Circuits and Systems
Publisher	IEEE Computer Society
Pages	51-59
Number of pages	9
ISBN (Print)	0-7695-0031-5
DOIs	https://doi.org/10.1109/ASYNC.1999.761522
Publication status	Published - 1999
Event	5th International Symposium on Advanced Research in Asynchronous Circuits and Systems - Barcelona, Spain Duration: 18 Apr 1999 → 22 Apr 1999 http://dblp.uni-trier.de/db/conf/async/async1999.html#LloydGG99http://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99

Conference

Conference	5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Abbreviated title	ASYNC '99
Country/Territory	Spain
City	Barcelona
Period	18/04/99 → 22/04/99
Internet address	http://dblp.uni-trier.de/db/conf/async/async1999.html#LloydGG99http://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99

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10.1109/ASYNC.1999.761522

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title = "AMULET3 revealed",

abstract = "AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Han'ard architecture to increase memory bandwidth and the inclusion of a reorder buffer to handle data forwarding and memory faults. {\textcopyright} 1999 IEEE.",

author = "Garside, {J. D.} and Furber, {S. B.} and Chung, {S. H.}",

year = "1999",

doi = "10.1109/ASYNC.1999.761522",

language = "English",

isbn = "0-7695-0031-5",

pages = "51--59",

booktitle = "Proceedings - International Symposium on Asynchronous Circuits and Systems",

publisher = "IEEE Computer Society ",

address = "United States",

note = "5th International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC '99 ; Conference date: 18-04-1999 Through 22-04-1999",

url = "http://dblp.uni-trier.de/db/conf/async/async1999.html#LloydGG99http://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/LloydGG99",

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AU - Furber, S. B.

AU - Chung, S. H.

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AB - AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Han'ard architecture to increase memory bandwidth and the inclusion of a reorder buffer to handle data forwarding and memory faults. © 1999 IEEE.

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DO - 10.1109/ASYNC.1999.761522

M3 - Conference contribution

SN - 0-7695-0031-5

SP - 51

EP - 59

BT - Proceedings - International Symposium on Asynchronous Circuits and Systems

PB - IEEE Computer Society

T2 - 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Y2 - 18 April 1999 through 22 April 1999

ER -

AMULET3 revealed

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