Abstract
A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presented. The architecture is based on a fine-grain software-programmable SIMD array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analogue microprocessor concept. In a 0.6pm CMOS process the cell size is equal to 98.6pmx98.6pm. A prototype 21x21 array chip executes over 1.1 GIPS (Giga Instructions Per Second) while dissipating below 40mW of power and demonstrates a real-time performance on a variety of early vision tasks.
| Original language | English |
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| Title of host publication | IEEE International Symposium on Circuits and Systems, ISCAS 2001 |
| Subtitle of host publication | 6-9 May 2001 |
| Place of Publication | New York |
| Publisher | IEEE |
| Pages | 490-493 |
| Number of pages | 4 |
| Volume | 4 |
| Publication status | Published - May 2001 |