An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

    Research output: Contribution to journalArticlepeer-review

    Abstract

    Massively parallel processor-per-pixel single-instruction multiple data arrays are being successfully used for early vision applications in smart sensor systems; however, they are inherently inefficient when executing algorithms involving propagation of binary signals, such as the geodesic reconstruction. Yet, these algorithms, at the interface between pixel-level and object-level image processing, should be implemented on the vision chip to facilitate data reduction at the sensor level. A cellular asynchronous network is presented in this paper, which can be used to execute binary propagation operations. The proposed circuit is optimized in terms of speed and power consumption. In 0.35-μm technology, the simulated propagation speed is 0.18 ns per pixel and the total energy expended per propagation is 0.37 pJ per cell. In this brief, implementation issues are discussed and simulation results including image processing examples are presented. © 2006 IEEE.
    Original languageEnglish
    Pages (from-to)354-358
    Number of pages4
    JournalIEEE Transactions on Circuits and Systems. Part 2: Express Briefs
    Volume53
    Issue number5
    DOIs
    Publication statusPublished - May 2006

    Keywords

    • Cellular arrays
    • Image processing
    • Parallel architectures
    • VLSI

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