Abstract
This paper presents an asynchronous on-chip network router with Quality-of-Service (QoS) support. The router uses a virtual channel architecture with a priority-based scheduler to differentiate between multiple connections with various QoS requirements sharing the same physical channel. A gate-level prototype of the router has been built and its functionality and performance evaluated. The simulations show that the router is capable of offering a high-level of QoS within the capacity limitations of the network.
Original language | English |
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Title of host publication | Proceedings - IEEE International SOC Conference |
Editors | J. Chickanosky, D. Ha, R. Auletta |
Pages | 274-277 |
Number of pages | 4 |
Publication status | Published - 2004 |
Event | Proceedings - IEEE International SOC Conference - Santa Clara, CA, United States Duration: 12 Sept 2004 → 15 Sept 2004 |
Conference
Conference | Proceedings - IEEE International SOC Conference |
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Country/Territory | United States |
City | Santa Clara, CA |
Period | 12/09/04 → 15/09/04 |