An event-driven model for the SpiNNaker virtual synaptic channel

Alexander Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp, Steve Furber

Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

Abstract

Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully satisfactory solution even though they have improved simulation performance, in part because of fixed hardware, in part because of poor software support. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. Central to this parallel multiprocessor is an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. In turn this requires an event-driven software model: a rethink as fundamental as that of the hardware. We examine this event-driven software model for an important hardware subsystem, the previously-introduced virtual synaptic channel. Using a scheduler-based system service architecture, the software can hide low-level processes and events from models so that the only event the model sees is "spike received". Results from simulation on-chip demonstrate the robustness of the system even in the presence of extremely bursty, unpredictable traffic, but also expose important model-evel tradeoffs that are a consequence of the physical nature of the SpiNNaker chip. This event-driven subsystem is the first component of a library-based development system that allows the user to describe a model in a high-level neural description environment and be able to rely on a lower layer of system services to execute the model efficiently on SpiNNaker. Such a system realises a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale. © 2011 IEEE.
Original languageEnglish
Title of host publicationProceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks
Place of PublicationUSA
PublisherIEEE
Pages1967-1974
Number of pages7
ISBN (Print)9781457710865
DOIs
Publication statusPublished - 2011
Event2011 International Joint Conference on Neural Network, IJCNN 2011 - San Jose, CA
Duration: 1 Jul 2011 → …
http://dx.doi.org/10.1109/IJCNN.2011.6033393

Conference

Conference2011 International Joint Conference on Neural Network, IJCNN 2011
CitySan Jose, CA
Period1/07/11 → …
Internet address

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