An instruction buffer for a low-power DSP

M. Lewis, L. Brackenbury

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    An architecture for a low-power asynchronous DSP has been developed, for the target application of GSM (digital cellphone) chipsets. A key part of this architecture is an instruction buffer which both provides storage for prefetched instructions and performs hardware looping. This requires low latency and a reasonably fast cycle time, but must also be designed for low power. A design is presented based on a word-slice FIFO structure. This avoids the problems of input latency and power consumption associated with linear micropipeline FIFOs, and the structure lends itself relatively easily to the required looping behaviour. The latency, cycle time and power consumption for this design is compared to that of a simple micropipeline FIFO. The cycle time for the instruction buffer is around three times slower than the micropipeline FIFO. However, the instruction buffer shows an energy per operation of between 48-62% of that for the (much less capable) micropipeline structure. The input to output latency with an empty FIFO is less than the micropipeline design by a facter of ten. © 2000 IEEE.
    Original languageEnglish
    Title of host publicationProceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.
    PublisherIEEE Computer Society
    Number of pages10
    Publication statusPublished - 2000
    Event6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 2000 - Eilat
    Duration: 1 Jul 2000 → …


    Conference6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 2000
    Period1/07/00 → …
    Internet address


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