Architectural optimization for low-power nonpipelined asynchronous systems

Luis A. Plana, Steven M. Nowick

    Research output: Contribution to journalArticlepeer-review


    This paper1 presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4. © 1998 IEEE.
    Original languageEnglish
    Pages (from-to)56-65
    Number of pages9
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number1
    Publication statusPublished - 1998


    • Asynchronous design
    • Data hazards
    • Handshaking
    • Hazards
    • Latches
    • Low power
    • Sequencers
    • Voltage scaling


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