Architectural optimization for low-power nonpipelined asynchronous systems

Luis A. Plana; Steven M. Nowick

doi:10.1109/92.661247

Architectural optimization for low-power nonpipelined asynchronous systems

Luis A. Plana, Steven M. Nowick

Research output: Contribution to journal › Article › peer-review

Abstract

This paper1 presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4. © 1998 IEEE.

Original language	English
Pages (from-to)	56-65
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	6
Issue number	1
DOIs	https://doi.org/10.1109/92.661247
Publication status	Published - 1998

Keywords

Asynchronous design
Data hazards
Handshaking
Hazards
Latches
Low power
Sequencers
Voltage scaling

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10.1109/92.661247

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@article{b12ab6bc5a8a4268b72cbc98f61f9ac2,

title = "Architectural optimization for low-power nonpipelined asynchronous systems",

abstract = "This paper1 presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4. {\textcopyright} 1998 IEEE.",

keywords = "Asynchronous design, Data hazards, Handshaking, Hazards, Latches, Low power, Sequencers, Voltage scaling",

author = "Plana, {Luis A.} and Nowick, {Steven M.}",

year = "1998",

doi = "10.1109/92.661247",

language = "English",

volume = "6",

pages = "56--65",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "IEEE",

number = "1",

}

TY - JOUR

T1 - Architectural optimization for low-power nonpipelined asynchronous systems

AU - Plana, Luis A.

AU - Nowick, Steven M.

PY - 1998

Y1 - 1998

N2 - This paper1 presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4. © 1998 IEEE.

AB - This paper1 presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4. © 1998 IEEE.

KW - Asynchronous design

KW - Data hazards

KW - Handshaking

KW - Hazards

KW - Latches

KW - Low power

KW - Sequencers

KW - Voltage scaling

U2 - 10.1109/92.661247

DO - 10.1109/92.661247

M3 - Article

SN - 1063-8210

VL - 6

SP - 56

EP - 65

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 1

ER -

Architectural optimization for low-power nonpipelined asynchronous systems

Abstract

Keywords

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