Architecture of a VLSI cellular processor array for synchronous/ asynchronous image processing

Alexey Lopich; Piotr Dudek

Architecture of a VLSI cellular processor array for synchronous/ asynchronous image processing

Alexey Lopich
, Piotr Dudek

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SEVID processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms. © 2006 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems\|Proc IEEE Int Symp Circuits Syst
Pages	3618-3621
Number of pages	3
Publication status	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos Duration: 1 Jul 2006 → …

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
City	Kos
Period	1/07/06 → …

Cite this

@inproceedings{87195f0be0c84288830ca992c7ccc6d0,

title = "Architecture of a VLSI cellular processor array for synchronous/ asynchronous image processing",

abstract = "This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SEVID processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms. {\textcopyright} 2006 IEEE.",

author = "Alexey Lopich and Piotr Dudek",

year = "2006",

language = "English",

isbn = "0780393902",

pages = "3618--3621",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 01-07-2006",

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TY - GEN

T1 - Architecture of a VLSI cellular processor array for synchronous/ asynchronous image processing

AU - Lopich, Alexey

AU - Dudek, Piotr

PY - 2006

Y1 - 2006

N2 - This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SEVID processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms. © 2006 IEEE.

AB - This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SEVID processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms. © 2006 IEEE.

M3 - Conference contribution

SN - 0780393902

SN - 9780780393905

SP - 3618

EP - 3621

BT - Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 1 July 2006

ER -

Architecture of a VLSI cellular processor array for synchronous/ asynchronous image processing

Abstract

Conference

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