This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit 'wave-propagation' or 'grassfire' transformation approach. A proof-of-concept design has been implemented and evaluated in FPGA and results are presented and discussed.
|Title of host publication||Proceedings of the 2005 European Conference on Circuit Theory and Design|Proc. 2005 Eur. Conf. Circ. Theory Design|
|Number of pages||3|
|Publication status||Published - 2005|
|Event||2005 European Conference on Circuit Theory and Design - Cork|
Duration: 1 Jul 2005 → …
|Conference||2005 European Conference on Circuit Theory and Design|
|Period||1/07/05 → …|