Architecture of asynchronous cellular processor array for image skeletonization

Aliaksei Lopich; Piotr Dudek

doi:10.1109/ECCTD.2005.1523065

Architecture of asynchronous cellular processor array for image skeletonization

Aliaksei Lopich, Piotr Dudek

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit 'wave-propagation' or 'grassfire' transformation approach. A proof-of-concept design has been implemented and evaluated in FPGA and results are presented and discussed.

Original language	English
Title of host publication	Proceedings of the 2005 European Conference on Circuit Theory and Design\|Proc. 2005 Eur. Conf. Circ. Theory Design
Pages	81-84
Number of pages	3
Volume	3
DOIs	https://doi.org/10.1109/ECCTD.2005.1523065
Publication status	Published - 2005
Event	2005 European Conference on Circuit Theory and Design - Cork Duration: 1 Jul 2005 → …

Conference

Conference	2005 European Conference on Circuit Theory and Design
City	Cork
Period	1/07/05 → …

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10.1109/ECCTD.2005.1523065

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title = "Architecture of asynchronous cellular processor array for image skeletonization",

abstract = "This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit 'wave-propagation' or 'grassfire' transformation approach. A proof-of-concept design has been implemented and evaluated in FPGA and results are presented and discussed.",

author = "Aliaksei Lopich and Piotr Dudek",

year = "2005",

doi = "10.1109/ECCTD.2005.1523065",

language = "English",

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note = "2005 European Conference on Circuit Theory and Design ; Conference date: 01-07-2005",

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AU - Dudek, Piotr

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N2 - This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit 'wave-propagation' or 'grassfire' transformation approach. A proof-of-concept design has been implemented and evaluated in FPGA and results are presented and discussed.

AB - This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit 'wave-propagation' or 'grassfire' transformation approach. A proof-of-concept design has been implemented and evaluated in FPGA and results are presented and discussed.

UR - https://www.scopus.com/pages/publications/33748987083

U2 - 10.1109/ECCTD.2005.1523065

DO - 10.1109/ECCTD.2005.1523065

M3 - Conference contribution

SN - 0780390660

SN - 9780780390669

VL - 3

SP - 81

EP - 84

BT - Proceedings of the 2005 European Conference on Circuit Theory and Design|Proc. 2005 Eur. Conf. Circ. Theory Design

T2 - 2005 European Conference on Circuit Theory and Design

Y2 - 1 July 2005

ER -

Architecture of asynchronous cellular processor array for image skeletonization

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