Abstract
This chapter describes the architecture and implementation of a digital vision chip, with asynchronous processing capabilities (asynchronous/synchronous processor array or ASPA). The discussion focuses on design aspects of cellular processor array with compact digital processing cell suitable for parallel image processing. The presented vision chip is based on an array of processing cells, each incorporating photo-sensor with a one-bit ADC and simple digital processor, which consists of 64-bit memory, arithmetic and logic unit (ALU), flag register and communication unit. The chip has two modes of operation: synchronous mode for local and nearest-neighbour operations and continuous-time mode for global operations. The speed of global image processing operations is significantly increased by using asynchronous processing techniques. In addition, the periphery circuitry enables asynchronous address extraction, fixed pattern addressing and flexible random access data I/O. © 2011 Springer Science+Business Media, LLC.
| Original language | English |
|---|---|
| Title of host publication | Focal-Plane Sensor-Processor Chips|Focal-Pl. Sens.-Process. Chips |
| Publisher | Springer Nature |
| Pages | 73-104 |
| Number of pages | 31 |
| DOIs | |
| Publication status | Published - 2011 |
Keywords
- Asynchronous image processing
- Cellular processor array
- Smart sensor
- Vision chip