ASPA: Focal plane digital processor array with asynchronous processing capabilities

Alexey Lopich; Piotr Dudek

doi:10.1109/ISCAS.2008.4541737

ASPA: Focal plane digital processor array with asynchronous processing capabilities

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing. A 19x22 proof-of-concept chip was fabricated and tested. At peak operational frequency (150MHz) each cell provides 9.6 MOPS thus achieving area utilization 820.8 MOPS/mm2 and power efficiency 29 GOPS/W. ©2008 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems\|Proc IEEE Int Symp Circuits Syst
Pages	1592-1595
Number of pages	3
DOIs	https://doi.org/10.1109/ISCAS.2008.4541737
Publication status	Published - 2008
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA Duration: 1 Jul 2008 → …

Conference

Conference	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
City	Seattle, WA
Period	1/07/08 → …

Access to Document

10.1109/ISCAS.2008.4541737

Cite this

@inproceedings{c870e9621b974fbfbe581be9983a49f4,

title = "ASPA: Focal plane digital processor array with asynchronous processing capabilities",

abstract = "In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing. A 19x22 proof-of-concept chip was fabricated and tested. At peak operational frequency (150MHz) each cell provides 9.6 MOPS thus achieving area utilization 820.8 MOPS/mm2 and power efficiency 29 GOPS/W. {\textcopyright}2008 IEEE.",

author = "Alexey Lopich and Piotr Dudek",

year = "2008",

doi = "10.1109/ISCAS.2008.4541737",

language = "English",

isbn = "9781424416844",

pages = "1592--1595",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst",

note = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 ; Conference date: 01-07-2008",

}

TY - GEN

T1 - ASPA: Focal plane digital processor array with asynchronous processing capabilities

AU - Lopich, Alexey

AU - Dudek, Piotr

PY - 2008

Y1 - 2008

N2 - In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing. A 19x22 proof-of-concept chip was fabricated and tested. At peak operational frequency (150MHz) each cell provides 9.6 MOPS thus achieving area utilization 820.8 MOPS/mm2 and power efficiency 29 GOPS/W. ©2008 IEEE.

AB - In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing. A 19x22 proof-of-concept chip was fabricated and tested. At peak operational frequency (150MHz) each cell provides 9.6 MOPS thus achieving area utilization 820.8 MOPS/mm2 and power efficiency 29 GOPS/W. ©2008 IEEE.

U2 - 10.1109/ISCAS.2008.4541737

DO - 10.1109/ISCAS.2008.4541737

M3 - Conference contribution

SN - 9781424416844

SP - 1592

EP - 1595

BT - Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst

T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

Y2 - 1 July 2008

ER -

ASPA: Focal plane digital processor array with asynchronous processing capabilities

Abstract

Conference

Access to Document

Fingerprint

Cite this