Automatic scan insertion and pattern generation for asynchronous circuits

Aristides Efthymiou, Christos Sotiriou, Douglas Edwards

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper presents 3φLSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3φLSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3φLSSD ATPG tool achieved over 99% test coverage.
    Original languageEnglish
    Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition|Proc. Des. Autom. Test Eur. Conf. Exhib
    EditorsG. Gielen, J. Figueras
    PublisherIEEE Computer Society
    Pages672-673
    Number of pages1
    Volume1
    ISBN (Print)0769520855, 9780769520858
    DOIs
    Publication statusPublished - 2004
    EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris
    Duration: 1 Jul 2004 → …

    Conference

    ConferenceProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
    CityParis
    Period1/07/04 → …

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