Abstract
To fully support the partial reconfiguration capabilities of FPGAs, this paper introduces the tool and API BitMan for generating and manipulating configuration bitstreams. Bit-Man supports recent Xilinx FPGAs that can be used by the ISE and Vivado tool suites of the FPGA vendor Xilinx, including latest Virtex-6, 7 Series, UltraScale and UltraScale- series FPGAs. The functionality includes high-level commands such as cutting out regions of a bitstream and placing or relocating modules on an FPGA as well as low-level commands for modifying primitives and for routing clock networks or rerouting signal connections at run-time. All this is possible without the vendor CAD tools for allowing BitMan to be used even with embedded CPUs. The paper describes the capabilities, API and performance evaluation of BitMan.
Original language | English |
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DOIs | |
Publication status | Published - 2017 |
Event | Design, Automation and Test in Europe (DATE) - Lausanne, Switzerland Duration: 27 Mar 2017 → 31 Mar 2017 https://www.date-conference.com/conference/event-overview |
Conference
Conference | Design, Automation and Test in Europe (DATE) |
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Country/Territory | Switzerland |
City | Lausanne |
Period | 27/03/17 → 31/03/17 |
Internet address |