Abstract
Network-on-chip (NoC) has been used as the new on- chip communication paradigm. Asynchronous NoCs are power efficient and robust to process variation but they are slow. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element and buffer trees introduced by the synchronization increase the cycle period. A new router is proposed to use multiple independent sub-channels to transmit data. Since the synchronization is removed, the cycle period of all sub-channels are reduced speeding up the network. Two routers, one using multiple independent sub-channels and one using the synchronized wide channel, are implemented at the layout level. The simulation results show that the new router using multiple independent sub-channels reduces the router latency and the cycle period. ©2009 IEEE.
| Original language | English |
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| Title of host publication | 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009|Int. Symp. System-on-Chip - Proc., SoC |
| Place of Publication | USA |
| Publisher | IEEE |
| Pages | 48-51 |
| Number of pages | 3 |
| ISBN (Print) | 9781424444670 |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 2009 International Symposium on System-on-Chip, SoC 2009 - Tampere Duration: 1 Jul 2009 → … |
Conference
| Conference | 2009 International Symposium on System-on-Chip, SoC 2009 |
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| City | Tampere |
| Period | 1/07/09 → … |
Keywords
- buffer circuits , integrated circuit layout , network-on-chip