TY - CONF
T1 - byteman: A Bitstream Manipulation Framework.
AU - Manev, Kristiyan
AU - Powell, Joseph
AU - Mätas, Kaspar
AU - Koch, Dirk
N1 - Funding Information:
This work is kindly supported by the Engineering and Physical Sciences Research Council (EPSRC) of the UK through project FORTE (grant agreement EPJR024642/1).
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - From better resource pooling for FPGA cloud providers to building dynamic execution pipelines at runtime, the capabilities of partial reconfiguration (PR) are waiting to be fully explored. However, the community still fails to materialize PR at scale, and FPGAs are only used as updatable ASICs, hence, omitting the opportunities offered by dynamically reconfiguring FPGAs at runtime. This work proposes a resourceful FPGA bitstream manipulation framework. The proposed tool provides means for parsing, modification, and generation of bitstream files, and it has been open-sourced and demonstrated in a working system. As a distinguished feature, it supports multidie FPGAs (among the 106 Xilinx 7 Series, UltraScale, and UltraScale+ devices), and enables datacenter FPGAs to be used for relocatable PR. Using the versatile tool's built-in (dis)assembler allows for manual bitstream manipulations. Bundled with an efficient bitstream manipulation core, the efficacy is demonstrated by two case studies where we observe 58 - 377x higher bitstream merging throughput than a current state-of-art tool.
AB - From better resource pooling for FPGA cloud providers to building dynamic execution pipelines at runtime, the capabilities of partial reconfiguration (PR) are waiting to be fully explored. However, the community still fails to materialize PR at scale, and FPGAs are only used as updatable ASICs, hence, omitting the opportunities offered by dynamically reconfiguring FPGAs at runtime. This work proposes a resourceful FPGA bitstream manipulation framework. The proposed tool provides means for parsing, modification, and generation of bitstream files, and it has been open-sourced and demonstrated in a working system. As a distinguished feature, it supports multidie FPGAs (among the 106 Xilinx 7 Series, UltraScale, and UltraScale+ devices), and enables datacenter FPGAs to be used for relocatable PR. Using the versatile tool's built-in (dis)assembler allows for manual bitstream manipulations. Bundled with an efficient bitstream manipulation core, the efficacy is demonstrated by two case studies where we observe 58 - 377x higher bitstream merging throughput than a current state-of-art tool.
KW - Bitstream Relocation
KW - FPGA
KW - Partial Reconfiguration
UR - http://www.scopus.com/inward/record.url?scp=85145571211&partnerID=8YFLogxK
U2 - 10.1109/ICFPT56656.2022.9974549
DO - 10.1109/ICFPT56656.2022.9974549
M3 - Paper
ER -