CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators

Geoffrey Ndu, Mikel Lujan, Javier Navaridas Palma

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    Abstract

    Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCl. We characterise CHO at various levels and use it to investigate compiling non-trivial software to FPGAs.
    Original languageEnglish
    Place of PublicationManchester, UK
    PublisherUniversity of Manchester
    Number of pages10
    Publication statusPublished - May 2014

    Publication series

    NameUniversity of Manchester Technical Report

    Keywords

    • FPGA
    • OpenCL
    • Software
    • Altera
    • Accelerator
    • High-level synthesis

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