Clock distribution models of 3-D integrated systems

Ioannis Savidis; Vasilis Pavlidis; Eby G. Friedman

doi:10.1109/ISCAS.2011.5938043

Clock distribution models of 3-D integrated systems

Ioannis Savidis
, Vasilis Pavlidis
, Eby G. Friedman

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved. © 2011 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems\|Proc IEEE Int Symp Circuits Syst
Publisher	IEEE
Pages	2225-2228
Number of pages	3
ISBN (Print)	9781424494736
DOIs	https://doi.org/10.1109/ISCAS.2011.5938043
Publication status	Published - 2011
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro Duration: 1 Jul 2011 → … http://dx.doi.org/10.1109/ISCAS.2011.5937774

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
City	Rio de Janeiro
Period	1/07/11 → …
Internet address	http://dx.doi.org/10.1109/ISCAS.2011.5937774

Keywords

CMOS integrated circuits , Clocks , Couplings , Reliability , Transistors

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10.1109/ISCAS.2011.5938043

Cite this

@inproceedings{56fde15b1126431f9e7b4cc84e356ddc,

title = "Clock distribution models of 3-D integrated systems",

abstract = "Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved. {\textcopyright} 2011 IEEE.",

keywords = "CMOS integrated circuits , Clocks , Couplings , Reliability , Transistors",

author = "Ioannis Savidis and Vasilis Pavlidis and Friedman, \{Eby G.\}",

year = "2011",

doi = "10.1109/ISCAS.2011.5938043",

language = "English",

isbn = "9781424494736",

pages = "2225--2228",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst",

publisher = "IEEE",

address = "United States",

note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 01-07-2011",

url = "http://dx.doi.org/10.1109/ISCAS.2011.5937774",

}

TY - GEN

T1 - Clock distribution models of 3-D integrated systems

AU - Savidis, Ioannis

AU - Pavlidis, Vasilis

AU - Friedman, Eby G.

PY - 2011

Y1 - 2011

N2 - Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved. © 2011 IEEE.

AB - Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved. © 2011 IEEE.

KW - CMOS integrated circuits , Clocks , Couplings , Reliability , Transistors

U2 - 10.1109/ISCAS.2011.5938043

DO - 10.1109/ISCAS.2011.5938043

M3 - Conference contribution

SN - 9781424494736

SP - 2225

EP - 2228

BT - Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst

PB - IEEE

T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

Y2 - 1 July 2011

ER -

Clock distribution models of 3-D integrated systems

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