Clock distribution networks for 3-D integrated circuits

Vasilis F. Pavlidis; Ioannis Savidis; Eby G. Friedman

doi:10.1109/CICC.2008.4672170

Clock distribution networks for 3-D integrated circuits

Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided. © 2008 IEEE.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference\|Proc Custom Integr Circuits Conf
Publisher	IEEE
Pages	651-654
Number of pages	3
DOIs	https://doi.org/10.1109/CICC.2008.4672170
Publication status	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA Duration: 1 Jul 2008 → …

Conference

Conference	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008
City	San Jose, CA
Period	1/07/08 → …

Keywords

Circuit testing , Circuit topology , Clocks , Integrated circuit interconnections , Laboratories
Manufacturing , Network topology , Power dissipation , Power measurement , Synchronization

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10.1109/CICC.2008.4672170

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title = "Clock distribution networks for 3-D integrated circuits",

abstract = "Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided. {\textcopyright} 2008 IEEE.",

keywords = "Circuit testing , Circuit topology , Clocks , Integrated circuit interconnections , Laboratories, Manufacturing , Network topology , Power dissipation , Power measurement , Synchronization",

author = "Pavlidis, {Vasilis F.} and Ioannis Savidis and Friedman, {Eby G.}",

year = "2008",

doi = "10.1109/CICC.2008.4672170",

language = "English",

pages = "651--654",

booktitle = "Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf",

publisher = "IEEE",

address = "United States",

note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 01-07-2008",

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TY - GEN

T1 - Clock distribution networks for 3-D integrated circuits

AU - Pavlidis, Vasilis F.

AU - Savidis, Ioannis

AU - Friedman, Eby G.

PY - 2008

Y1 - 2008

N2 - Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided. © 2008 IEEE.

AB - Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided. © 2008 IEEE.

KW - Circuit testing , Circuit topology , Clocks , Integrated circuit interconnections , Laboratories

KW - Manufacturing , Network topology , Power dissipation , Power measurement , Synchronization

U2 - 10.1109/CICC.2008.4672170

DO - 10.1109/CICC.2008.4672170

M3 - Conference contribution

SP - 651

EP - 654

BT - Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf

PB - IEEE

T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 1 July 2008

ER -

Clock distribution networks for 3-D integrated circuits

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