Clock distribution networks for 3-D integrated circuits

Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


    Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided. © 2008 IEEE.
    Original languageEnglish
    Title of host publicationProceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf
    Number of pages3
    Publication statusPublished - 2008
    EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA
    Duration: 1 Jul 2008 → …


    ConferenceIEEE 2008 Custom Integrated Circuits Conference, CICC 2008
    CitySan Jose, CA
    Period1/07/08 → …


    • Circuit testing , Circuit topology , Clocks , Integrated circuit interconnections , Laboratories
    • Manufacturing , Network topology , Power dissipation , Power measurement , Synchronization


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