Clock distribution networks in 3-D integrated systems

Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

    Research output: Contribution to journalArticlepeer-review


    3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes. © 2006 IEEE.
    Original languageEnglish
    Article number5599895
    Pages (from-to)2256-2266
    Number of pages10
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number12
    Publication statusPublished - Dec 2011


    • 3-D clock characterization
    • 3-D clock distribution
    • 3-D clock modeling
    • 3-D synchronization


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