Abstract
This paper introduces a mapping method for adding a coarse grain (multiple pixels per processor) processing mode to massively parallel cellular processor arrays. The main motivation is to provide the fine grain pixel-parallel processor array with the ability of processing images with higher resolution than the array itself, in a way that is transparent to the programmer. The proposed method accomplishes the mapping work entirely during the code compilation process, which has four main advantages. Firstly, there is no extra overhead during processing. Secondly, the source code for fine grain mode can be used in coarse grain mode without modification. Thirdly, the proposed method does not introduce any restrictions of the number of pixels stored in a processing element. Finally, the proposed method is easy to implement, as it does not require any modifications to the hardware design of the pixel-parallel processor array or its controller, but only to the software compiler. The mapping method and its software implementation are presented in this paper. © 2012 IEEE.
| Original language | English |
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| Title of host publication | International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl. |
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| Publication status | Published - 2012 |
| Event | 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 - Turin Duration: 1 Jul 2012 → … |
Conference
| Conference | 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 |
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| City | Turin |
| Period | 1/07/12 → … |